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R
Enhanced SCSI Bus Controller
AIC -33C94
TM
(R)
Overview
The Adaptec AIC-33C94 Enhanced SCSI Bus Controller (ESBC) is ideal for the needs of today's peripheral systems. SCSI command automation coupled with custom programmability provides a flexible solution for OEM designers. These features, integrated into a system with Adaptec host systems, deliver end-to-end compatibility and leading-edge performance.
in bytes or blocks, enables larger data transfers to be performed with a single command. Programming flexibility The AIC-33C94 controllers can handle SCSI protocol and data transfer through a 128-word Writable Control Store (WCS), which allows developers to program any sequence of SCSI bus phases. The AIC-33C94 controller can act as a target as well as an initiator. Simplified development An advantage of the AIC-33C94 controller is ease of development. An evaluation kit is available that helps speed time to market. It includes an evaluation board with sample WCS, SCSI, and SCAM Level 1 and Level 2 codes that can be quickly customized. Easy-to-follow flow charts and application notes provide step-by-step programming guidance. Either target or initiator mode can be emulated for evaluation and debugging. Power management For implementations where power consumption is an issue, the AIC-33C94 controller features an automatic sleep mode. If the controller is idle for a specified period of time, it powers down. It goes back into operation within 200 nanoseconds. This feature is beneficial for portable-based applications.
Key Benefits Product Highlights
n Synchronous
SCSI data transfer rate up to 10 MBps 128-word Writable Control Store for handling SCSI protocol and data transfer for SCSI Configured automatically (SCAM) protocol with low-level SCSI bus control architecture with dedicated 8-bit microprocessor interface and integrated DMA controller, programmable to be bus master or slave by 9-bit dual port registers to store commands, messages, and status
n Programmable
n Support
n Split-bus
Fast, efficient data transfer The AIC-33C94 ESBC controls data transfers between the 8-bit SCSI bus and the local data buffer. A splitbus architecture provides separate CPU and DMA buses that enable concurrent operations for optimum performance. The CPU bus is a dedicated 8-bit microprocessor interface. The 16-bit DMA bus is programmable to handle either 8-bit or 16-bit transfers, delivering a maximum data transfer rate of 10 MBps in 8-bit mode or 20 MBps in 16-bit mode. The total time required to perform arbitration, selection, command transfer, and message transfer is less than 20 microseconds. A 32-byte on-chip RAM buffer enables the storage of command, message, and status bytes, reducing code development and ensuring more efficient operation by reducing the burden on the CPU. A pipelined 24-bit transfer counter, specifiable
n 32-word
AIC-33C94 FEATURES SUMMARY
Adaptec, Inc. 691 South Milpitas Boulevard Milpitas, California 95035 Tel: (408) 945-8600 Fax: (408) 262-2533 Adaptec Europe - Belgium Tel: (32) 2-352-34-11 Fax: (32) 2-352-34-00 Adaptec Japan - Tokyo Tel: (81) 3-5365-6700 Fax: (81) 3-5365-6950 Adaptec Singapore Tel: (65) 278-7300 Fax: (65) 273-0163 Literature: 1-800-934-2766 (USA and Canada) or (510) 732-3829 Pre-Sales Support: 1-800-442-7274 (USA and Canada) or (408) 957-7274 World Wide Web: http://www.adaptec.com Internet ftp server: ftp.adaptec.com Adaptec USA Bulletin Board Service (BBS): (408) 945-7727 (up to 28,800 baud, using 8 bits, 1 stop bit, no parity) Interactive Fax: (303) 684-3400
Task File MICROPROCESSOR
AIC-33C94 ESBC Technical Information
Features: * Automatic response to a bus-initiated selection/reselection * 16-word FIFO to support synchronous offset up to 32 bytes * Programmable synchronous transfer period * Pipelined 24-bit transfer counter * Transfers that can be specified in bytes or logical blocks * Microprocessor that also accesses the internal registers through the DMA bus * All the signals needed for users to interface 8-bit differential bus * Power-down mode if not active Tape drives CD-ROMs Printers Scanners Copiers DVDs Analyzers Voice mail Instrumentation 100-pin MQFP
Applications:
Packaging:
Design Support Tools: Demo94 Board WCS assembler and sample codes SCAM sample codes Sample schematics Application Notes
RE WE CS ALE AD (7-0)
Micro. Interface
R
BIDIR Buffer
Dual Port Regs. 32 x 9
BIDIR Buffer
ID
DWE DMA BUS DRE DREQ DACK DMA Control Logic Writable Control Store 128 x 30 SCSI Protocol Control SCSI Control Sig.
Copyright 1998 Adaptec, Inc. All rights reserved. Adaptec, the Adaptec logo, and AIC are trademarks of Adaptec, Inc., which may be registered in some jurisdictions. All other trademarks used are owned by their respective owners. Information supplied by Adaptec, Inc. is believed to be accurate and reliable at the time of printing, but Adaptec, Inc. assumes no responsibility for any errors that may appear in this document. Adaptec, Inc. reserves the right, without notice, to make changes in product design or specifications. Information is subject to change without notice. P/N 980289-021 Printed in U.S.A. 3/98
BD (15-0) BDPL, BDPH
BIDIR Buffer
16 x 18 FIFO
SD (7-0), SDP
AIC-33C94 Enhanced SCSI Bus Controller Architecture

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